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74VHCT573ANX View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
74VHCT573ANX
Fairchild
Fairchild Semiconductor Fairchild
74VHCT573ANX Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
Pin Descriptions
Truth Table
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Outputs
Functional Description
The VHCT573A contains eight D-type latches with 3-
STATE output buffers. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW the latches store the information that was present on
Inputs
OE
LE
L
H
L
H
L
L
H
X
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Outputs
D
On
H
H
L
L
X
O0
X
Z
the D inputs, a setup time preceding the HIGH-to-LOW
transition of LE. The 3-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers
are enabled. When OE is HIGH the buffers are in the high
impedance mode, but, this does not interfere with entering
new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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