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74LVX3245 View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
74LVX3245 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
Physical Dimensions
24
B
7 .5 0 ±0 .1 0
10.325
1 5 .40 ±0 .2 0
13.970
A
13
14.52
10.95
9.2
1
PIN ONE
IN D IC A T O R
0.51
0.35
0.25 M C B A
12
1.27
1.75 TYP
1.27 TYP
0.55 TYP
LAND PATTERN RECOM M ENDATION
2.65 MAX
(R 0 .1 0 )
(R 0 .1 0 )
0.40~1.27
(1.40)
0 .20±0.10
0.75
0.25
X 45°
C
0.10 C
GAGE PLANE
0.25
SEATING PLANE
DETAIL A
SCALE: 2:1
SEE DETAIL A
0.33
0.20
SEATING PLANE
NOTES: UNLESS OTHERW ISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, ISSUE E, DATED SEPT 2005.
B) ALL DIM ENSIONS ARE IN MILLIMETERS.
C) DIM ENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATERN STANDARD: SOIC127P1030X265-24L
E) DRAW ING FILENAME: MKT-M24BREV2
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may
change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fair-
child Semiconductor representative to verify or obtain the most recent revision. Package specifications do not
expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
www.fairchildsemi.com
6
 

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