datasheetbank_Logo     Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

74LVQ240 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
74LVQ240 LOW VOLTAGE OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (INVERTED) ST-Microelectronics
STMicroelectronics ST-Microelectronics
74LVQ240 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
74LVQ240
LOW VOLTAGE OCTAL BUS BUFFER
WITH 3 STATE OUTPUTS (INVERTED)
s HIGH SPEED:
tPD = 6 ns (TYP.) at VCC = 3.3 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s LOW NOISE:
VOLP = 0.4V (TYP.) at VCC = 3.3V
s 75TRANSMISSION LINE OUTPUT DRIVE
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 240
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ240 is a low voltage CMOS OCTAL
BUS BUFFER fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ240MTR
74LVQ240TTR
technology. It is ideal for low power and low noise
3.3V applications.
G output control governs four BUS BUFFERs.
This device is designed to be used with 3 state
memory address drivers, etc.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 7
1/12
Direct download click here

 

Share Link : 

All Rights Reserved © datasheetbank.com 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]