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74LVQ240QSC View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
74LVQ240QSC Datasheet PDF : 6 Pages
1 2 3 4 5 6
May 1998
74LVQ240
Low Voltage Octal Buffer/Line Driver with 3-STATE
Outputs
General Description
The LVQ240 is an inverting octal buffer and line driver de-
signed to be employed as a memory address driver, clock
driver and bus oriented transmitter or receiver which pro-
vides improved PC board density.
Features
n Ideal for low power/low noise 3.3V applications
n Implements patented EMI reduction circuitry
n Available in SOIC JEDEC, SOIC EIAJ, and QSOP
packages
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75
n 4 kV minimum ESD immunity
Ordering Code:
Order Number
74LVQ240SC
74LVQ240SJ
74LVQ240QSC
Package Number
M20B
M20D
MQA20
Package Description
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC
20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Assignment,
SOIC and QSOP
Pin Descriptions
DS011611-1
Pin Names
OE1, OE2
I0– I7
O0– O7
Description
3-STATE Output Enable Inputs
Inputs
Outputs
© 1998 Fairchild Semiconductor Corporation DS011611
Truth Tables
DS011611-2
Inputs
OE1
In
L
L
L
H
H
X
Outputs
(Pins 12, 14, 16, 18)
H
L
Z
Inputs
Outputs
OE2
In
L
L
(Pins 3, 5, 7, 9)
H
L
H
L
H
X
Z
H = HIGH Voltage Level
X = Immaterial
L = LOW Voltage Level
Z = High Impedance
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