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54F/74F299 View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
54F/74F299 Octal Universal Shift/Storage Register with Common Parallel I/O Pins National-Semiconductor
National ->Texas Instruments National-Semiconductor
54F/74F299 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9515 – 3
TL F 9515–2
Unit Loading Fan Out
Pin Names
CP
DS0
DS7
S0 S1
MR
OE1 OE2
I O0 – I O7
Q0 Q7
Description
Clock Pulse Input (Active Rising Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset Input (Active LOW)
TRI-STATE Output Enable Inputs (Active LOW)
Parallel Data Inputs or
TRI-STATE Parallel Outputs
Serial Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
10 20
10 10
10 10
3 5 1 083
150 40(33 3)
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b1 2 mA
20 mA b0 6 mA
20 mA b0 6 mA
70 mA b0 65 mA
b3 mA 24 mA (20 mA)
b1 mA 20 mA
Functional Description
The ’F299 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
shift left shift right parallel load and hold operations The
type of operation is determined by S0 and S1 as shown in
the Mode Select Table All flip-flop outputs are brought out
through TRI-STATE buffers to separate I O pins that also
serve as data inputs in the parallel load mode Q0 and Q7
are also brought out on other pins for expansion in serial
shifting of longer words
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops All other state changes are initiated
by the rising edge of the clock Inputs can change when the
clock is in either state provided only that the recommended
setup and hold times relative to the rising edge of CP are
observed
A HIGH signal on either OE1 or OE2 disables the TRI-
STATE buffers and puts the I O pins in the high impedance
state In this condition the shift hold load and reset opera-
tions can still occur The TRI-STATE outputs are also dis-
abled by HIGH signals on both S0 and S1 in preparation for
a parallel load operation
Mode Select Table
Inputs
MR S1 S0 CP
Response
L X X X Asynchronous Reset Q0 – Q7 e LOW
x H H H L Parallel Load I On Qn
x x H L H L Shift Right DS0
Q0 Q0
Q1 etc
x x H H L L Shift Left DS7
Q7 Q7
Q6 etc
H L L X Hold
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW-to-HIGH Clock Transition
2
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