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1SV241 View Datasheet(PDF) - NXP Semiconductors.

Part NameDescriptionManufacturer
1SV241 RF Manual 16th edition NXP
NXP Semiconductors. NXP
1SV241 Datasheet PDF : 130 Pages
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1. Products by application
1.1 Wireless communication infrastructure
1.1.1 Base stations (all cellular standards and frequencies)
See also brochure: 'Your partner in Mobile Communication Infrastructure design', NXP document number 9397 750 16837.
Application diagram
Digital
Front
End
DPD
CFR
DUC
DDC
Dual
DAC
I
PLL
VCO
IQ-Modulator
DVGA RF-BP MPA
0
90
Power Amplifier
HPA
Q
JEDEC
IF
ADC
Transmitter
IF-SAW DVGA Mixer+LO
Att.
LO
Dual
ADC
BP or LP
Dual
DVGA
IF-SAW
Dual
Mixer
RF-SAW
PLL
VCO
LNA Filter Unit
Tower -
Mounted
Amplifier
Tx
LNA +VGA
Rx
µC
LNA+VGA
TX / RX1
RX2
Clock
Generator
Jitter Cleaner
Data Converter RF Small Signal
RF Power
Micro Controller
The block diagram above shows transmit (upper part, Tx) and receive (lower part, Rx) functions of a base station, and includes the Tx feedback function (middle part, Tx feedback).
The signals generated in the "Digital Baseband & Control" block follow the requirements of the air-interface standard. These signals are interfaced to the DAC via
serial interface SER. The SER can use the LVDS or JEDEC standard. After the signals are fed to the I-DAC and Q-DAC, they are converted to the analog domain.
Before the I and Q signals enter the IQ modulator, they are first low-pass filtered to remove any aliasing signals. At the IQ modulator, the signals are up-converted to
RF using an LO signal coming from the PLL/VCO device, typically called the LO generator. Due to device aging and variation in cell load, the up-converted signals
are fed to the VGA to control the power level. An additional band-pass filter is needed to remove the out-of-band spurs. The clean signal is fed to the RF power
board, where the desired transmit power is made. Finally, the RF power signal is fed to the antenna via a duplexer.
Directly after the final-stage amplifier, a signal coupler picks up a certain amount of the RF signal, which is attenuated and then down-mixed using the IF mixer.
This signal is called the observation signal, and is used to derive coefficients for the digital pre-distortion algorithm. Since power levels vary, the observation is first
fed to the VGA to control the power level, and after band-pass filtering, the signal is converted to the digital domain using an ADC. The same serial interface is used
to send the digital signals to the baseband processor.
At the receiver, the received signal directly after the duplexer is fed to the LNA for direct amplification, since the received signal level is quite low. If the first LNA
is mounted in the tower top, a long RF cable is used to interface the RF signals with a base transceiver station (BTS). A second LNA is used to amplify the received
signals. Band-pass filtering is applied to reduce the out-of-band signals levels before these signals are applied to the IF mixer. Signal levels that change dramatically
require a VGA to maintain the full scale ranges of the I-ADC and Q-ADC for optimal conversion performance. Low-pass filtering is used before the ADC to remove
the aliasing signals. These digital signals are interfaced to the baseband using a serial interface such as JEDEC.
The sample clocks and LO signals are derived from clock cleaners and PLLs respectively. This is denoted as Clock and PLL / VCO in the block diagram. This set-up
is required to make a synchronized system. Typically denoted in SNRs, and in order to improve reception quality, the receive function is equipped with a second
receiver, called a diversity receiver.
NXP Semiconductors RF Manual 16th edition
9
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