MC145149 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

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MC145149

Dual PLL Frequency Synthesizer

Motorola => Freescale 

PIN DESCRIPTIONS

INPUT PINS

OSCin, OSCout

Reference Oscillator Input/Output (Pins 15, 16)

These pins form a reference oscillator when connected to

terminals of an external parallel–resonant crystal. Fre-

quency–setting capacitors of appropriate value must be con-

nected from OSCin and OSCout to ground.

OSCin may also serve as input for an externally–generated

reference signal. The signal is typically ac coupled to OSCin,

but for signals with CMOS logic levels, dc coupling may be

used. When used with an external reference, OSCout should

be left open.

fin1, fin2

Frequency Inputs (Pins 4, 7)

Input frequency from an external VCO output. Each rising–

edge signal on fin1 decrements the N counter, and when ap-

propriate, the A counter of PLL 1. Similarly, fin2 decrements

the counters of PLL 2.

These inputs have inverters biased on the linear region

which allows ac coupling for signals as low as 500 mV p–p.

With square wave signals which swing from VSS to VDD, dc

coupling may be used.

DATA, CLK

Data, Clock Inputs (Pins 5, 6)

Shift register data and clock inputs. Each low–to–high

transition on the clock pin shifts one bit of data into the on–

chip shift registers. Refer to Figure 7 for the following discus-

sion.

The last bit entered is a steering bit that determines which

set of latches are activated. A logic high selects the latches

for PLL 1. A logic low selects PLL 2.

The second–to–last bit controls the appropriate port ex-

pander output, SW1 or SW2. A logic low forces the output

low. A logic high forces the output to the high–impedance

state.

The third–to–last bit determines which storage latch is acti-

vated. A logic low selects the ÷ A and ÷ N counter latches. A

logic high selects the reference counter latch.

When writing to either set of ÷ A and ÷ N counter latches,

20 clock cycles are typically used. However, if a byte–

oriented MCU is utilized, 24 clock cycles may be used with

the first 4 bits being “Don’t Care.”

When writing to either reference counter latch, 17 clock

cycles are typically used. However, if a byte–oriented MCU is

utilized, 24 clock cycles may be used with the first 7 bits

being “Don’t Care”.

ENB

Latch Enable Input (Pin 3)

A positive pulse on this input transfers data from the shift

registers to the selected latches, as determined by the con-

trol and steering data bits. A logic low level on this pin allows

the user to shift data into the shift registers without affecting

the data in the latches or counters. Enable is normally held

low and is pulsed high to transfer data into the latches.

OUTPUT PINS

PDout1, PDout2

Single–Ended Phase Detector Outputs (Pins 19, 12)

Each single–ended (three–state) phase detector output

produces a loop error signal that is used with a loop filter to

control a VCO (see Figure 8).

Frequency fV > fR or fV Leading: Negative Pulses

Frequency fV < fR or fV Lagging: Positive Pulses

Frequency fV = fR and Phase Coincidence: High–Imped-

ance State

S/Rout

Shift Register Output (Pin 8)

This output can be connected to an external shift register

to provide band switching or control information. S/Rout may

also be used to check the counter programming bit stream.

MC1, MC2

Modulus Control Outputs (Pins 2, 9)

Each output generates a signal by the on–chip control

logic circuitry for controlling an external dual–modulus

prescaler. The modulus control level is low at the beginning

of a count cycle and remains low until the ÷ A counter has

counted down from its programmed value. At this time,

modulus control goes high and remains high until the ÷ N

counter has counted the rest of the way down from its

programmed value (N–A additional counts since both ÷ N

and ÷ A are counting down during the first portion of the

cycle). Modulus control is then set back low, the counters are

preset to their respective programmed values, and the above

sequence is repeated. This provides for a total program-

mable divide value (NT) = N • P + A where P and P + 1 repre-

sent the dual–modulus prescaler divide values respectively

for high and low modulus control levels, N the number pro-

grammed into the ÷ N counter, and A the number pro-

grammed into the ÷ A counter.

Note that when a prescaler is needed, the dual–modulus

version offers a distinct advantage. The dual–modulus

prescaler allows a higher reference frequency at the phase

detector input, increasing system performance capability,

and simplifying the loop filter design.

LD1, LD2

Lock Detect Signals (Pins 1, 10)

Each output is essentially at a high logic level when the

corresponding loop is locked (fR and fV of the same phase

and frequency). Each output pulses low when the corre-

sponding loop is out of lock (see Figure 8).

SW1, SW2

Latched Open–Drain Switch Outputs (Pins 17, 14)

The state of each output is controlled by the “SW STATE”

bit shown in Figure 7. If the bit is a logic high, the correspond-

ing SW output assumes the high–impedance state. If the bit

is low, the SW output goes low.

To control output SW1, steering bit PLL 1/PLL 2 shown in

Figure 7 must be high. To control SW2, bit PLL 1/PLL 2 must

be low.

These outputs have an output voltage range of VSS to

15 V.

MC145149

6

MOTOROLA

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