MC145149 View Datasheet(PDF) - Motorola => Freescale
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MC145149 Datasheet PDF : 12 Pages
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DUAL–MODULUS PRESCALING
OVERVIEW
The technique of dual–modulus prescaling is well estab-
lished as a method of achieving high performance frequency
synthesizer operation at high frequencies. Basically, the
approach allows relatively low–frequency programmable
counters to be used as high–frequency programmable
counters with speed capability of several hundred MHz. This
is possible without the sacrifice in system resolution and per-
formance that results if a fixed (single–modulus) divider is
used for the prescaler.
In dual–modulus prescaling, the lower speed counters
must be uniquely configured. Special control logic is nec-
essary to select the divide value P or P + 1 in the prescaler
for the required amount of time (see modulus control defi-
nition). Motorola’s dual–modulus frequency synthesizers
contain this feature and can be used with a variety of dual–
modulus prescalers to allow speed, complexity, and cost to
be tailored to the system requirements. Prescalers having P,
P + 1 divide values in the range of ÷ 3/÷ 4 to ÷ 128/÷ 129 can
be controlled by most Motorola frequency synthesizers.
Several dual–modulus prescaler approaches suitable for
use with the MC145149 are:
MC12009
MC12011
MC12013
MC12015
MC12016
MC12017
MC12018
MC12022A
MC12032A
÷ 5/÷ 6
÷ 8/÷ 9
÷ 10 / ÷ 11
÷ 32 / ÷ 33
÷ 40 / ÷ 41
÷ 64 / ÷ 65
÷ 128 / ÷ 129
÷ 64 / 65 or ÷ 128 / 129
÷ 64 / 65 or ÷ 128 / 129
440 MHz
500 MHz
500 MHz
225 MHz
225 MHz
225 MHz
520 MHz
1.1 GHz
2.0 GHz
DESIGN GUIDELINES
The system total divide value, Ntotal (NT) will be dictated by
the application, i.e.,
frequency into the prescaler
NT = frequency into the phase detector = N P + A
N is the number programmed into the ÷ N counter, A is the
number programmed into the ÷ A counter, P and P + 1 are
the two selectable divide ratios available in the dual–modu-
lus prescalers. To have a range of NT values in sequence,
the ÷ A counter is programmed from 0 through P – 1 for a
particular value N in the ÷ N counter. N is then incremented
to N + 1 and the ÷ A is sequenced from 0 through P – 1
again.
There are minimum and maximum values that can be
achieved for NT. These values are a function of P and the
size of the ÷ N and ÷ A counters.
The constraint N ≥ A always applies. If Amax = P – 1, then
Nmin ≥ P – 1. Then NTmin = (P – 1) P + A or (P – 1) P since A
is free to assume the value of 0.
NTmax = Nmax P + Amax
To maximize system frequency capability, the dual–modu-
lus prescaler output must go from low to high after each
group of P or P + 1 input cycles. The prescaler should divide
by P when its modulus control line is high and by P + 1 when
its modulus control is low.
For the maximum frequency into the prescaler (fVCO max),
the value used for P must be large enough such that:
1. fVCO max divided by P may not exceed the frequency
capability of fin (input to the ÷ N and ÷ A counters).
2. The period of fVCO divided by P must be greater than
the sum of the times:
a. Propagation delay through the dual–modulus
prescaler.
b. Prescaler setup or release time relative to its
modulus control signal.
c. Propagation time from fin to the modulus control
output for the frequency synthesizer device.
A sometimes useful simplification in the programming
code can be achieved by choosing the values for P of 8, 16,
32, or 64. For these cases, the desired value of NT results
when NT in binary is used as the program code to the ÷ N
and ÷ A counters treated in the following manner:
1. Assume the ÷ A counter contains “a” bits where 2a ≥ P.
2. Always program all higher order ÷ A counter bits above
“a” to 0.
3. Assume the ÷ N counter and the ÷ A counter (with all the
higher order bits above “a” ignored) combined into a
single binary counter of n + a bits in length (n = number
of divider stages in the ÷ N counter). The MSB of this “hy-
pothetical” counter is to correspond to the MSB of ÷ N
and the LSB is to correspond to the LSB of ÷ A. The sys-
tem divide value, NT, now results when the value of NT
in binary is used to program the “new” n + a bit counter.
By using the two devices, several dual–modulus values
are achievable.
MC
DEVICE A
DEVICE B
DEVICE
B
DEVICE A
MC12009
MC10131 ÷ 20/÷ 21
MC10138 ÷ 50/÷ 51
MC10154
÷ 40/÷ 41
OR
÷ 80/÷ 81
MC12011
÷ 32/÷ 33
÷ 80/÷ 81
÷ 64/÷ 65
OR
÷ 128/÷ 129
MC12013
÷ 40/÷ 41
÷ 100/÷ 101
÷ 80/÷ 81
NOTE: MC12009, MC12011, and MC12013 are pin equivalent.
MC12015, MC12016, and MC12017 are pin equivalent.
MC145149
10
MOTOROLA
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