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T-8503-GL2-D View Datasheet(PDF) - Agere -> LSI Corporation

Part NameDescriptionManufacturer
T-8503-GL2-D Dual PCM codec with filters. Tape and reel. Agere
Agere -> LSI Corporation Agere
T-8503-GL2-D Datasheet PDF : 16 Pages
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Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Pin Information (continued)
Table 1. Pin Descriptions
Symbol Pin Type*
Name/Function
VFXIN1 20
VFXIN0 1
I Voice Frequency Transmitter Input. Analog inverting input to the uncommitted oper-
ational amplifier at the transmit filter input. Connect the signal to be digitized to this pin
through a resistor RI (see Figure 2).
GSX1 19 O Gain Set for Transmitter. Output of the transmit uncommitted operational amplifier.
GSX0
2
The pin is the input to the transmit differential filters. Connect the pin to its
corresponding VFXIN through a resistor RF (see Figure 2).
VFRO1 17
VFRO0 4
O Voice Frequency Receiver Output. This pin can drive 2000 (or greater) loads.
VDD
6
+5 V Power Supply. This pin should be bypassed to ground with at least 0.1 µF of
capacitance as close to the device as possible.
GNDA1 18
GNDA0 3
Analog Grounds. All ground pins must be connected on the circuit board.
DR
12
I Receive PCM Data Input. The data on this pin is shifted into the device on the falling
edges of MCLK. Data is only entered for valid time slots as defined by the FSR inputs.
DX
11 O Transmit PCM Data Output. This pin remains in the high-impedance state except
during active transmit time slots. An active transmit time slot is defined as one in which
a pulse is present on one of the FSX inputs. Data is shifted out on the rising edge of
MCLK.
MCLK 9
I Master Clock Input. The frequency must be 2.048 MHz or 4.096 MHz. This clock
serves as the bit clock for all PCM data transfer.
GNDD 10
Digital Ground. Ground connection for the digital circuitry. All ground pins must be
connected on the circuit board.
FSX1 13 Id Transmit Frame Sync. This signal is an edge trigger and must be high for a minimum
FSX0
8
of one MCLK cycle. This signal must be derived from MCLK. The division ratio is 1:256
or 1:512 (FSX:MCLK). Each FSX input must have a pulse present at the start of the
desired active output time slot. Pulses on FSX inputs must be separated by one or more
integer multiples of time slots. If the device is to be used as an A/D converter only, FSX
must be tied to FSR. An internal pull-down device is included on each FSX.
FSR1 14 Id Receive Frame Sync. This signal is an edge trigger and must be high for a minimum
FSR0
7
of one MCLK cycle. This signal must be derived from MCLK. The division ratio is 1:256
or 1:512 (FSR:MCLK). Each FSR input must have a pulse present at the start of the
desired active input time slot. Pulses on FSR inputs must be separated by one or more
integer multiples of time slots. If the device is to be used as a D/A converter only, FSR
must be tied to FSX. An internal pull-down device is included on each FSR.
GS1 16 Iu Gain Selection. A high or floating state sets the receive path gain at 0 dB; a logic low
GS0
5
sets the gain to –3.5 dB. A pull-up device is included.
ASEL 15
Id A-Law/µ-Law Select. A logic low selects µ-law coding. A logic high selects A-law
coding. A pull-down device is included.
* Id indicates a pull-down device is included on this lead. Iu indicates a pull-up device is included on this lead.
Lucent Technologies Inc.
3
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