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T-8503-GL2-D View Datasheet(PDF) - Agere -> LSI Corporation

Part NameDescriptionManufacturer
T-8503-GL2-D Dual PCM codec with filters. Tape and reel. Agere
Agere -> LSI Corporation Agere
T-8503-GL2-D Datasheet PDF : 16 Pages
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Data Sheet
July 1998
T8502 and T8503 Dual PCM Codecs with Filters
Features
s +5 V only
s Two independent channels
s Pin-selectable receive gain control
s Pin-selectable µ-law or A-law companding
s Automatic powerdown mode
s Low-power, latch-up-free CMOS technology
— 40 mW/channel typical operating power
dissipation
— 12.5 mW/channel typical standby power
dissipation
s Automatic master clock frequency selection
— 2.048 MHz or 4.096 MHz
s Independent transmit and receive frame strobes
s 2.048 MHz or 4.096 MHz data rate
s On-chip sample and hold, autozero, and precision
voltage reference
s Differential architecture for high noise immunity
and power supply rejection
s Meets or exceeds ITU-T G.711—G.714 require-
ments and VF characteristics of D3/D4 (as per
Bellcore PUB43801)
s Operating temperature range: –40 °C to +85 °C
Description
The T8502 and T8503 devices are single-chip, two-
channel, µ-law/A-law PCM codecs with filters. These
integrated circuits provide analog-to-digital and
digital-to-analog conversion. They provide the
transmit and receive filtering necessary to interface a
voice telephone circuit to a time-division multiplexed
system. These devices are packaged in both 20-pin
SOJs and 20-pin SOGs.
The T8502 differs from the T8503 in its timing mode.
The T8502 operates in the delayed timing mode
(digital data is valid one clock cycle after frame sync
goes high), and the T8503 operates in the
nondelayed timing mode (digital data valid when
frame sync goes high) (see Figures 5 and 6).
GSX0
VFXIN0
+
+2.4 V
FILTER
NETWORK
CHANNEL 0
ENCODER
PCM
INTERFACE
DX
DR
FSX0
FSR0
FSX1
FSR1
GNDD
VFRO0
GSX1
VFXIN1
VFRO1
FILTER
NETWORK
DECODER
CHANNEL 1
GAIN
CONTROL
INTERNAL TIMING
& CONTROL
BIAS
CIRCUITRY
&
REFERENCE
Figure 1. Block Diagram
GS0
GS1
MCLK
ASEL
VDD
GNDA (2)
5-3579.b
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