FAN5236MTC View Datasheet(PDF) - Fairchild Semiconductor
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FAN5236MTC Datasheet PDF : 20 Pages
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FAN5236
PRODUCT SPECIFICATION
Circuit Description
Overview
The FAN5236 is a multi-mode, dual channel PWM control-
ler intended for graphic chipset, SDRAM, DDR DRAM or
other low voltage power applications in modern notebook,
desktop, and sub-notebook PCs. The IC integrates a control
circuitry for two synchronous buck converters. The output
voltage of each controller can be set in the range of 0.9V to
5.5V by an external resistor divider.
The two synchronous buck converters can operate from
either an unregulated DC source (such as a notebook battery)
with voltage ranging from 5.0V to 24V, or from a regulated
system rail of 3.3V to 5V. In either mode of operation the IC
is biased from a +5V source. The PWM modulators use an
average current mode control with input voltage feed-for-
ward for simplified feedback loop compensation and
improved line regulation. Both PWM controllers have inte-
grated feedback loop compensation that dramatically
reduces the number of external components.
Depending on the load level, the converters can operate
either in fixed frequency PWM mode or in a hysteretic mode.
Switch-over from PWM to hysteretic mode improves the
converters’ efficiency at light loads and prolongs battery run
time. In hysteretic mode, comparators are synchronized to
the main clock that allows seamless transition between the
operational modes and reduced channel-to-channel interac-
tion. The hysteretic mode of operation can be inhibited inde-
pendently for each channel if variable frequency operation is
not desired.
The FAN5236 can be configured to operate as a complete
DDR solution. When the DDR pin is set high, the second
channel can provide the capability to track the output voltage
of the first channel. The PWM2 converter is prevented from
going into hysteretic mode if the DDR pin is set high. In
DDR mode, a buffered reference voltage (buffered voltage of
the REF2 pin), required by DDR memory chips, is provided
by the PG2 pin.
Converter Modes and Synchronization
Table 3. Converter modes and Synchronization
Mode VIN
DDR PWM 2 w.r.t.
VIN Pin Pin PWM1
DDR1
DDR2
DUAL
Battery
+5V
ANY
VIN
R to GND
VIN
HIGH
HIGH
LOW
IN PHASE
+ 90°
+ 180°
When used as a dual converter (as in Figure 5), out-of-phase
operation with 180 degree phase shift reduces input current
ripple.
For the “2-step” conversion (where the VTT is converted
from VDDQ as in Figure 4) used in DDR mode, the duty
cycle of the second converter is nominally 50% and the opti-
mal phasing depends on VIN. The objective is to keep noise
generated from the switching transition in one converter
from influencing the "decision" to switch in the other con-
verter.
When VIN is from the battery, it’s typically higher than 7.5V.
As shown in Figure 6, 180° operation is undesirable since
the turn-on of the VDDQ converter occurs very near the
decision point of the VTT converter.
CLK
VDDQ
VTT
Figure 6. Noise-susceptible 180° phasing for DDR1
In-phase operation is optimal to reduce inter-converter inter-
ference when VIN is higher than 5V, (when VIN is from a
battery), as can be seen in Figure 7. Since the duty cycle
of PWM1 (generating VDDQ) is short, it’s switching point
occurs far away from the decision point for the VTT
regulator, whose duty cycle is nominally 50%.
CLK
VDDQ
VTT
Figure 7. Optimal In-Phase operation for DDR1
When VIN ≈ 5V, 180° phase shifted operation can be
rejected for the same reasons demonstrated Figure 6.
In-phase operation with VIN ≈ 5V is even worse, since the
switch point of either converter occurs near the switch point
of the other converter as seen in Figure 8. In this case, as
VIN is a little higher than 5V it will tend to cause early
termination of the VTT pulse width. Conversely, VTT’s
switch point can cause early termination of the VDDQ pulse
width when VIN is slightly lower than 5V.
REV. 1.1.9 7/12/04
9
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