74AC109 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
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74AC109 Datasheet PDF : 6 Pages
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MC74AC109
MC74ACT109
Dual JK Positive
EdgeĆTriggered FlipĆFlop
The MC74AC109/74ACT109 consists of two high-speed completely independent
transition clocked JK flip-flops. The clocking operation is independent of rise and fall
times of the clock waveform. The JK design allows operation as a D flip-flop (refer to
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs
VCC CD2 J2 K2 CP2 SD2 Q2 Q2
16 15 14 13 12 11 10 9
CD
J
K
CP
SD
Q
Q
CD1
J1
K1
CP1 SD1
Q1
Q1
12
CD1 J1
3456
K1 CP1 SD1 Q1
78
Q1 GND
PIN NAMES
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
TRUTH TABLE
Inputs
Outputs
SD CD CP J
K
Q
Q
L
HXX X H
L
H
LXX X L
H
L
LXX X H
H
H
H
LLL
H
H
H
HL
Toggle
H
H
H
H
L H Q0 Q0-
HHH
L
H
HLX
X Q0 Q0-
H = HIGH Voltage Level
L = LOW Voltage Level
= LOW-to-HIGH Clock Transition
X = Immaterial
Q0(Q0) = Previous Q0(Q0) before
LOW-to-HIGH Transition of Clock
DUAL JK POSITIVE
EDGE-TRIGGERED
FLIP-FLOP
N SUFFIX
CASE 648-08
PLASTIC
D SUFFIX
CASE 751B-05
PLASTIC
LOGIC SYMBOL
Q
Q
SD
CD
J CP K
Q
Q
SD
CD
J CP K
FACT DATA
5-1
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