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54F109LCX View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
54F109LCX Dual JK Positive Edge-Triggered Flip-Flop National-Semiconductor
National ->Texas Instruments National-Semiconductor
54F109LCX Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
Pin Assignment
for LCC
DS009471-1
DS009471-2
Unit Loading/Fan Out
See Section 0 for U.L. definitions
DSXXX
54F/74F
Pin Names
Description
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Data Inputs
Clock Pulse Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−1.8 mA
20 µA/−1.8 mA
−1 mA/20 mA
Truth Table
Inputs
Outputs
SD
CD
CP
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H
H
H
H
N
l
l
L
H
H
H
N
h
l
Toggle
H
H
N
l
h
Q0
Q0
H
H
N
h
h
H
L
H
H
L
X
X
Q0
Q0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
N = LOW-to-HIGH Transition
X = Immaterial
Q0 (Q0) = Before LOW-to-HIGH Transition of Clock
Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
www.national.com
2
PrintDate=1997/08/28 PrintTime=11:45:23 10182 ds009471 Rev. No. 1 cmserv Proof
2
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