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MT29F64G08CFABAWP View Datasheet(PDF) - Micron Technology

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MT29F64G08CFABAWP Datasheet PDF : 160 Pages
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Micron Confidential and Proprietary
32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
General Description
General Description
Micron NAND Flash devices include an asynchronous data interface for high-perform-
ance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer
commands,address, and data. There are five control signals used to implement the asyn-
chronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection (WP#) and monitor device status (R/B#).
This Micron NAND Flash device additionally includes a synchronous data interface for
high-performance I/O operations. When the synchronous interface is active, WE# be-
comes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe
(DQS).
This hardware interface creates a low pin-count device with a standard pinout that re-
mains the same from one density to another, enabling future upgrades to higher densi-
ties with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the ONFI specification, is
referred to as a logical unit (LUN). For further details, see Device and Array Organization.
Asynchronous and Synchronous Signal Descriptions
Table 1: Asynchronous and Synchronous Signal Definitions
Asynchronous
Signal1
ALE
Synchronous
Signal1
ALE
CE#
CE#
CLE
CLE
DQx
DQx
DQS
RE#
W/R#
WE#
CLK
WP#
R/B#
VCC
WP#
R/B#
VCC
Type
Input
Input
Input
I/O
I/O
Input
Input
Input
Output
Supply
Description2
Address latch enable: Loads an address from DQx into the address reg-
ister.
Chip enable: Enables or disables one or more die (LUNs) in a target1.
Command latch enable: Loads a command from DQx into the com-
mand register.
Data inputs/outputs: The bidirectional I/Os transfer address, data, and
command information.
Data strobe: Provides a synchronous reference for data input and out-
put.
Read enable and write/read: RE# transfers serial data from the NAND
Flash to the host system when the asynchronous interface is active.
When the synchronous interface is active, W/R# controls the direction of
DQx and DQS.
Write enable and clock: WE# transfers commands, addresses, and seri-
al data from the host system to the NAND Flash when the asynchronous
interface is active. When the synchronous interface is active, CLK latches
command and address cycles.
Write protect: Enables or disables array PROGRAM and ERASE opera-
tions.
Ready/busy: An open-drain, active-low output that requires an exter-
nal pull-up resistor. This signal indicates target array activity.
VCC: Core power supply
PDF: 09005aef836c9ded
Rev. F 12/09 EN
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
 

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