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MT29F64G08CFABAWP View Datasheet(PDF) - Micron Technology

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MT29F64G08CFABAWP Datasheet PDF : 160 Pages
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Micron Confidential and Proprietary
32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
Bus Operation – Synchronous Interface
ALE and CLE are latched LOW on the rising edge of CLK
The final two data bytes of the data input sequence are written to DQ[7:0] to the
cache register on the rising and falling edges of DQS after the last cycle in the data
input sequence in which ALE and CLE are latched HIGH.
DQS is held LOW for tWPST (after the final falling edge of DQS)
Following tWPST, the bus enters bus idle mode and tCAD begins on the next rising edge
of CLK. After tCAD starts, the host can disable the target if desired.
Data input is ignored by die (LUNs) that are not selected or are busy.
Figure 33: Synchronous DDR Data Input Cycles
CE#
CLE
ALE
CLK
W/R#
DQS
DQ[7:0]
tCS
tCH
tCALS
tCALS
tCKL tCKH
tCAD
tCALS
tCALS
tCK
tCALS
tCALH
tCALS
tCALH
tCALH
tCALH
tCAD
starts
here1
tDQSS
tDSH tDSS tDSH
tDSH tDSS tDSH tDSS
tWPRE
tDQSH tDQSL tDQSH
tDQSL tDQSH
tWPST
D0
D1
D2
D3
tDS
tDH
DN-2 DN-1
DN
tDS
tDH
Don’t Care
Notes:
1. When CE# remains LOW, tCAD begins at the first rising edge of the clock after tWPST
completes.
2. tDSH (MIN) generally occurs during tDQSS (MIN).
3. tDSS (MIN) generally occurs during tDQSS (MAX).
Synchronous DDR Data Output
Data can be output from a die (LUN) if it is ready. Data output is supported following a
READ operation from the NAND Flash array.
To enter the DDR data output mode, the following conditions must be met:
CLK is running
CE# is LOW
The host has released the DQ[7:0] bus and DQS
W/R# is latched LOW on the rising edge of CLK to enable the selected die (LUN) to
take ownership of the DQ[7:0] bus and DQS within tWRCK
tCAD is met
ALE and CLE are HIGH on the rising edge of CLK
PDF: 09005aef836c9ded
Rev. F 12/09 EN
42
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
 

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