MT29F64G08CFABAWP View Datasheet(PDF) - Micron Technology

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MT29F64G08CFABAWP

Asynchronous/Synchronous NAND NAND Flash Memory / 52-pad LGA / 48-pin TSOP / 100-ball BGA

Micron Technology 

Micron Confidential and Proprietary

32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND

Bus Operation – Asynchronous Interface

Asynchronous Data Output

Data can be output from a die (LUN) if it is in a READY state. Data output is supported

following a READ operation from the NAND Flash array. Data is output from the cache

register of the selected die (LUN) to DQ[7:0] on the falling edge of RE# when CE# is

LOW, ALE is LOW, CLE is LOW, and WE# is HIGH.

If the host controller is using a tRC of 30ns or greater, the host can latch the data on the

rising edge of RE# (see Figure 22 for proper timing). If the host controller is using a tRC

of less than 30ns, the host can latch the data on the next falling edge of RE# (see Fig-

ure 23 (page 32) for extended data output (EDO) timing).

Using the READ STATUS ENHANCED (78h) command prevents data contention follow-

ing an interleaved die (multi-LUN) operation. After issuing the READ STATUS EN-

HANCED (78h) command, to enable data output, issue the READ MODE (00h) command.

Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); howev-

er, it is possible to output data from the status register even when a die (LUN) is busy by

first issuing the READ STATUS (70h) or READ STATUS ENHANCED (78h) command.

Figure 22: Asynchronous Data Output Cycles

CE#

RE#

DQx

RDY

tCEA

tREA

tRP

tREH

tREA

tREA

tCHZ

tCOH

Dout

tRR

tRC

tRHZ

Dout

tRHZ

tRHOH

Dout

Don’t Care

PDF: 09005aef836c9ded

Rev. F 12/09 EN

31

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2008 Micron Technology, Inc. All rights reserved.

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