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MT29F64G08CFABAWP View Datasheet(PDF) - Micron Technology

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32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
Bus Operation – Asynchronous Interface
Bus Operation – Asynchronous Interface
The asynchronous interface is active when the NAND Flash device powers on. The I/O
bus, DQ[7:0], is multiplexed sharing data I/O, addresses, and commands. The DQS sig-
nal, if present, is tri-stated when the asynchronous interface is active.
Asynchronous interface bus modes are summarized below.
Table 3: Asynchronous Interface Mode Selection
Mode
Standby
Bus idle
Command input
CE#
CLE
ALE
WE#
RE#
DQS
DQx
WP#
Notes
H
X
X
X
X
X
X
0V/VCCQ2
2
L
X
X
H
H
X
X
X
L
H
L
H
X
input
H
Address input
L
L
H
H
X
input
H
Data input
L
L
L
H
X
input
H
Data output
L
L
L
H
X
output
X
Write protect
X
X
X
X
X
X
X
L
Notes:
1. DQS is tri-stated when the asynchronous interface is active.
2. WP# should be biased to CMOS LOW or HIGH for standby.
3. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH
or VIL.
Asynchronous Enable/Standby
A chip enable (CE#) signal is used to enable or disable a target. When CE# is driven
LOW, all of the signals for that target are enabled. With CE# LOW, the target can accept
commands, addresses, and data I/O. There may be more than one target in a NAND
Flash package. Each target is controlled by its own chip enable; the first target (Target 0)
is controlled by CE#; the second target (if present) is controlled by CE2#, etc.
A target is disabled when CE# is driven HIGH, even when the target is busy. When disa-
bled, all of the target's signals are disabled except CE#, WP#, and R/B#. This functionali-
ty is also known as CE# "Don't Care". While the target is disabled, other devices can
utilize the disabled NAND signals that are shared with the NAND Flash.
A target enters low-power standby when it is disabled and is not busy. If the target is
busy when it is disabled, the target enters standby after all of the die (LUNs) complete
their operations. Standby helps reduce power consumption.
Asynchronous Bus Idle
A target's bus is idle when CE# is LOW, WE# is HIGH, and RE# is HIGH.
During bus idle, all of the signals are enabled except DQS, which is not used when the
asynchronous interface is active. No commands, addresses, and data are latched into
the target; no data is output.
PDF: 09005aef836c9ded
Rev. F 12/09 EN
27
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
 

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