74HC00BQ-Q100 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
View to exact match
74HC00BQ-Q100 Datasheet PDF : 15 Pages
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Nexperia
74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
5. Pinning information
5.1 Pinning
+&4
+&74
$
%
<
$
%
<
*1'
9&&
%
$
<
%
$
<
DDD
Fig 4. Pin configuration SO14 and TSSOP14
+&4
+&74
WHUPLQDO
LQGH[DUHD
%
<
$
%
<
*1'
%
$
<
%
$
DDD
7UDQVSDUHQWWRSYLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
6. Functional description
Description
data input
data input
data output
ground (0 V)
supply voltage
Table 3. Function table[1]
Input
nA
nB
L
X
X
L
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Output
nY
H
H
L
74HC_HCT00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 November 2015
© Nexperia B.V. 2017. All rights reserved
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