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74HCT174N View Datasheet(PDF) - NXP Semiconductors.

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Description
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74HCT174N Datasheet PDF : 18 Pages
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NXP Semiconductors
74HC174; 74HCT174
Hex D-type flip-flop with reset; positive-edge trigger
6. Functional description
Table 3. Function table[1]
Operating modes
Inputs
MR
CP
Dn
reset (clear)
L
X
X
load “1”
H
h
load “0”
H
l
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
7. Limiting values
Outputs
Qn
L
H
L
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
0.5
+7
V
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
[1] -
20
mA
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
[1] -
20
mA
IO
output current
0.5 V < VO < VCC + 0.5 V
-
25
mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
Tamb = 40 C to +125 C
DIP16 package
-
50
65
[2] -
50
mA
-
mA
+150
C
750
mW
SO16, SSOP16 and TSSOP16
[3] -
500
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP16 package: above 70 C the value of Ptot derates linearly with 12 mW/K.
[3] For SO16 package: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
74HC_HCT174
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 16 April 2013
© NXP B.V. 2013. All rights reserved.
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