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74HC74D View Datasheet(PDF) - NXP Semiconductors.

Part Name74HC74D NXP
NXP Semiconductors. NXP
DescriptionDual D-type flip-flop with set and reset; positive edge-trigger
74HC74D Datasheet PDF : 21 Pages
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NXP Semiconductors
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Min Typ[1] Max
VOH
VOL
II
ICC
ICC
HIGH-level
output voltage
LOW-level
output voltage
input leakage
current
supply current
additional
supply current
VI = VIH or VIL; VCC = 4.5 V
IO = 4 mA
VI = VIH or VIL; VCC = 4.5 V
IO = 4.0 mA
VI = VCC or GND;
VCC = 5.5 V
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
VI = VCC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
per input pin; nD, nRD
inputs
3.84
-
-
-
-
4.32
0.15
-
-
70
-
0.33
1.0
40
315
per input pin; nSD, nCP
-
input
80
360
CI
input
3.5
capacitance
Tamb = 40 C to +125 C
Min
Max
3.7
-
-
0.4
-
1.0
-
80
-
343
-
392
Unit
V
V
A
A
A
A
pF
[1] All typical values are measured at Tamb = 25 C.
74HC_HCT74
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 27 August 2012
© NXP B.V. 2012. All rights reserved.
6 of 21
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The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.

The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual
data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has
complementary outputs (Q andQ).

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