74HC74CU View Datasheet(PDF) - NXP Semiconductors.
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Description
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74HC74CU Datasheet PDF : 21 Pages
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NXP Semiconductors
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
6. Functional description
Table 3. Function table[1]
Input
nSD
nRD
nCP
nD
L
H
X
X
H
L
X
X
L
L
X
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Output
nQ
nQ
H
L
L
H
H
H
Table 4. Function table[1]
Input
nSD
nRD
nCP
nD
H
H
L
H
H
H
Output
nQn+1
L
H
nQn+1
H
L
[1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition;
X = don’t care.
7. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
DIP14 package
SO14, (T)SSOP14 and DHVQFN14
packages
0.5 +7
V
-
20 mA
-
20 mA
-
25 mA
-
+100 mA
100 -
mA
65 +150 C
[1] -
750 mW
[1] -
500 mW
[1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT74
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 27 August 2012
© NXP B.V. 2012. All rights reserved.
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