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74HC74D View Datasheet(PDF) - NXP Semiconductors.

Part Name74HC74D NXP
NXP Semiconductors. NXP
DescriptionDual D-type flip-flop with set and reset; positive edge-trigger
74HC74D Datasheet PDF : 21 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
NXP Semiconductors
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
5. Pinning information
5.1 Pinning
5' 
' 
&3 
6' 
4 
4 
*1' 
+&
+&7
 9&&
 5'
 '
 &3
 6'
 4
 4
DDD
Fig 5. Pin configuration for DIP14, SO14 and (T)SSOP14
+&
+&7
WHUPLQDO 
LQGH[ DUHD
'
&3 
6' 
4 
4 
*1' 
 5'
 '
 &3
 6'
 4
DDD
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There
is no electrical or mechanical requirement to solder
this pad. However, if it is soldered, the solder land
should remain floating or be connected to GND.
Fig 6. Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
VCC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
asynchronous reset-direct input (active LOW)
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
output
complement output
ground (0 V)
complement output
output
asynchronous set-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
asynchronous reset-direct input (active LOW)
supply voltage
74HC_HCT74
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 27 August 2012
© NXP B.V. 2012. All rights reserved.
3 of 21
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The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.

The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual
data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has
complementary outputs (Q andQ).

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