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74HC74D View Datasheet(PDF) - NXP Semiconductors.

Part Name74HC74D NXP
NXP Semiconductors. NXP
DescriptionDual D-type flip-flop with set and reset; positive edge-trigger


74HC74D Datasheet PDF : 21 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
NXP Semiconductors
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
VI 90 %
negative
pulse
GND
VI
positive
pulse
10 %
GND
VM
10 %
tf
tr
90 %
VM
VI
G
RT
tW
tW
VCC
DUT
VM
tr
tf
VM
VO
CL
001aah768
Fig 9.
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Test circuit for measuring switching times
Table 10. Test data
Type
Input
74HC74
74HCT74
VI
tr, tf
VCC
6 ns
3V
6 ns
Load
CL
15 pF, 50 pF
15 pF, 50 pF
RL
1 k
1 k
Test
tPLH, tPHL
tPLH, tPHL
74HC_HCT74
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 27 August 2012
© NXP B.V. 2012. All rights reserved.
12 of 21
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The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.

The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual
data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has
complementary outputs (Q andQ).

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