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29F64G08CBAAA View Datasheet(PDF) - Micron Technology

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29F64G08CBAAA
Micron
Micron Technology Micron
29F64G08CBAAA Datasheet PDF : 159 Pages
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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Activating Interfaces
Activating Interfaces
After performing the steps under Device Initialization (page 46), the asynchronous inter-
face is active for all targets on the device.
Each target's interface is independent of other targets, so the host is responsible for
changing the interface for each target.
If the host and NAND Flash device, through error, are no longer using the same inter-
face, then steps under Activating the Asynchronous Interface are performed to re-
synchronize the interfaces.
Activating the Asynchronous Interface
To activate the asynchronous NAND interface, once the synchronous interface is active,
the following steps are repeated for each target:
1. The host pulls CE# HIGH, disables its input to CLK, and enables its asynchronous
interface.
2. The host pulls CE# LOW and issues the RESET (FFh) command, using an asynchro-
nous command cycle.
3. R/B# goes LOW for tRST.
4. After tITC, and during tRST, the device enters the asynchronous NAND interface.
READ STATUS (70h) and READ STATUS ENHANCED (78h) are the only com-
mands that can be issued.
5. After tRST, R/B# goes HIGH. Timing mode feature address (01h), subfeature param-
eter P1 is set to 00h, indicating that the asynchronous NAND interface is active
and that the device is set to timing mode 0.
For further details, see Reset Operations.
Activating the Synchronous Interface
To activate the synchronous NAND Flash interface, the following steps are repeated for
each target:
1. Issue the SET FEATURES (EFh) command.
2. Write address 01h, which selects the timing mode.
3. Write P1 with 1Xh, where "X" is the timing mode used in the synchronous inter-
face (see Configuration Operations).
4. Write P2–P4 as 00h-00h-00h.
5. R/B# goes LOW for tITC. The host should pull CE# HIGH. During tITC, the host
should not issue any type of command, including status commands, to the NAND
Flash device.
6. After tITC, R/B# goes HIGH and the synchronous interface is enabled. Before pull-
ing CE# LOW, the host should enable the clock.
PDF: 09005aef83d2277a
Rev. A 11/09 EN
47
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009 Micron Technology, Inc. All rights reserved.
 

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