|29F64G08CBAAA||NAND Flash Memory|
|29F64G08CBAAA Datasheet PDF : 159 Pages |
Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Some NAND Flash devices do not support VCCQ. For these devices all references to VCCQ
are replaced with VCC.
Micron NAND Flash devices are designed to prevent data corruption during power tran-
sitions. VCC is internally monitored. (The WP# signal supports additional hardware
protection during power transitions.) When ramping VCC and VCCQ, use the following
procedure to initialize the device:
1. Ramp VCC.
2. Ramp VCCQ. VCCQ must not exceed VCC.
3. The host must wait for R/B# to be valid and HIGH before issuing RESET (FFh) to
any target (see Figure 35). The R/B# signal becomes valid when 50µs has elapsed
since the beginning the VCC ramp, and 10µs has elapsed since VCCQ reaches VCCQ
(MIN) and VCC reaches VCC (MIN).
4. If not monitoring R/B#, the host must wait at least 100µs after VCCQ reaches VCCQ
(MIN) and VCC reaches VCC (MIN). If monitoring
R/B#, the host must wait until R/B# is HIGH.
5. The asynchronous interface is active by default for each target. Each LUN draws
less than an average of 10mA (IST) measured over intervals of 1ms until the RESET
(FFh) command is issued.
6. The RESET (FFh) command must be the first command issued to all targets (CE#s)
after the NAND Flash device is powered on. Each target will be busy for tPOR after
a RESET command is issued. The RESET busy time can be monitored by polling
R/B# or issuing the READ STATUS (70h) command to poll the status register.
7. The device is now initialized and ready for normal operation.
At power-down, VCCQ must go LOW, either before, or simultaneously with, VCC going
Figure 35: R/B# Power-On Behavior
Vccq = Vccq (MIN)
Vcc = Vcc (MIN)
Note: 1. Disregard VCCQ for devices that use only VCC.
Rev. A 11/09 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009 Micron Technology, Inc. All rights reserved.
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