29F64G08CBAAA View Datasheet(PDF) - Micron Technology
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29F64G08CBAAA Datasheet PDF : 159 Pages
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Micron Confidential and Proprietary
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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Bus Operation – Synchronous Interface
Figure 34: Synchronous DDR Data Output Cycles
CE#
CLE
ALE
CLK
W/R#
DQS
DQ[7:0]
tCS
tCALS
tCALS
tCKL tCKH
tCAD
tCK
tCALS
tWRCK
tDQSD
tCALS
tCALS
tCALS
tCALH
tCALS
tCALH
tHP tHP tHP
tHP tHP tHP
tDQSCK
tDQSCK
tDQSCK
tDQSCK
tCKWR
tDQSCK
tDQSCK
tCH
tCLH
tALH
tCAD starts
here1
tCALS tDQSHZ
tAC
tDQSQ
tDVW tDVW tDVW
D0
D1
D2
tDQSQ
tQH tQH
tDVW tDVW
DN-2
tDQSQ
DN-1
tQH
DN
tDQSQ
tQH
Undefined (driven by NAND)
Don’t Care
Data Transitioning
Notes:
1. When CE# remains LOW, tCAD begins at the rising edge of the clock after tCKWR for
subsequent command or data output cycle(s).
2. See Figure 31 (page 41) for details of W/R# behavior.
3. tAC is the DQ output window relative to CLK and is the long-term component of DQ skew.
4. For W/R# transitioning HIGH, DQ[7:0] and DQS go to tri-state.
5. For W/R# transitioning LOW, DQ[7:0] drives current state and DQS goes LOW.
6. After final data output, DQ[7:0] is driven until W/R# goes HIGH, but is not valid.
Write Protect
See Write Protect (page 33).
Ready/Busy#
See Ready/Busy# (page 33).
PDF: 09005aef83d2277a
Rev. A 11/09 EN
45
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009 Micron Technology, Inc. All rights reserved.
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