29F64G08CBAAA View Datasheet(PDF) - Micron Technology

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29F64G08CBAAA

NAND Flash Memory

Micron Technology 

Micron Confidential and Proprietary

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND

Bus Operation – Synchronous Interface

Upon entering the DDR data output mode, DQS will toggle HIGH and LOW with a delay

of tDQSCK from the respective rising and falling edges of CLK. DQ[7:0] will output data

edge-aligned to the rising and falling edges of DQS, with the first transition delayed by

no more than tAC.

DDR data output mode continues as long as CLK is running, CE# is LOW, W/R# is LOW,

and ALE and CLE are HIGH on the rising edge of CLK.

To exit DDR data output mode, the following conditions must be met:

• CLK is running

• CE# is LOW

• W/R# is LOW

• ALE and CLE are latched LOW on the rising edge of CLK

The final two data bytes are output on DQ[7:0] on the final rising and falling edges of

DQS. The final rising and falling edges of DQS occur tDQSCK after the last cycle in the

data output sequence in which ALE and CLE are latched HIGH. After tCKWR, the bus

enters bus idle mode and tCAD begins on the next rising edge of CLK. Once tCAD starts

the host can disable the target if desired.

Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); howev-

er, it is possible to output data from the status register even when a die (LUN) is busy by

issuing the READ STATUS (70h) or READ STATUS ENHANCED (78h) command.

PDF: 09005aef83d2277a

Rev. A 11/09 EN

44

Micron Technology, Inc. reserves the right to change products or specifications without notice.

©2009 Micron Technology, Inc. All rights reserved.

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