|29F64G08CBAAA||NAND Flash Memory|
|29F64G08CBAAA Datasheet PDF : 159 Pages |
Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Bus Operation – Synchronous Interface
Figure 30: Synchronous Bus Idle/Driving Behavior
Undefined (driven by NAND)
Note: 1. Only the selected die (LUN) drives DQS and DQ[7:0]. During an interleaved die (multi-
LUN) operation, the host must use the READ STATUS ENHANCED (78h) to prevent data
A command is written from DQ[7:0] to the command register on the rising edge of CLK
when CE# is LOW, ALE is LOW, CLE is HIGH, and W/R# is HIGH.
After a command is latched—and prior to issuing the next command, address, or
data I/O—the bus must go to bus idle mode on the next rising edge of CLK, except
when the clock period, tCK, is greater than tCAD.
Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
commands, such as READ STATUS (70h) and READ STATUS ENHANCED (78h), are ac-
cepted by die (LUNs), even when they are busy.
Rev. A 11/09 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009 Micron Technology, Inc. All rights reserved.
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