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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Bus Operation – Synchronous Interface
Bus Operation – Synchronous Interface
These NAND Flash devices have two interfaces—a synchronous interface for fast data
I/O transfer and an asynchronous interface that is backward compatible with existing
NAND Flash devices.
The NAND Flash command protocol for both the asynchronous and synchronous inter-
faces is identical. However, there are some differences betweeen the asynchronous and
synchronous interfaces when issuing command, address, and data I/O cycles using the
NAND Flash signals.
When the synchronous interface is activated on a target (see Activating Interfaces
(page 47)), the target is capable of high-speed DDR data transfers. Existing signals are
redefined for high-speed DDR I/O. The WE# signal becomes CLK. DQS is enabled. The
RE# signal becomes W/R#. CLK provides a clock reference to the NAND Flash device.
DQS is a bidirectional data strobe. During data output, DQS is driven by the NAND
Flash device. During data input, DQS is controlled by the host controller while input-
ting data on DQ[7:0].
The direction of DQS and DQ[7:0] is controlled by the W/R# signal. When the W/R# sig-
nal is latched HIGH, the controller is driving the DQ bus and DQS. When the W/R# is
latched LOW, the NAND Flash is driving the DQ bus and DQS.
The synchronous interface bus modes are summarized below.
Table 4: Synchronous Interface Mode Selection
Mode
CE#
CLE
ALE
CLK
Standby
H
X
X
X
Bus idle
L
L
L
Bus driv-
L
L
L
ing
Command
L
H
L
input
Address
L
L
H
input
Data input
L
H
H
Data out-
L
H
H
put
Write pro-
X
X
X
X
tect
Undefined
L
L
H
Undefined
L
H
L
W/R#
X
H
L
H
H
H
L
X
L
L
DQS
X
X
output
DQ[7:0]
X
X
output
WP#
0V/VCCQ
X
X
X
input
H
X
input
H
input
H
See Note 5 output
X
X
X
L
output
output
X
output
output
X
Notes
1, 2
3
3
4
5
Notes:
1. CLK can be stopped when the target is disabled, even when R/B# is LOW.
2. WP# should be biased to CMOS LOW or HIGH for standby.
3. Commands and addresses are latched on the rising edge of CLK.
4. During data input to the device, DQS is the “clock” that latches the data in the cache
register.
PDF: 09005aef83d2277a
Rev. A 11/09 EN
38
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