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29F64G08CBAAA View Datasheet(PDF) - Micron Technology

Part NameDescriptionManufacturer
29F64G08CBAAA NAND Flash Memory Micron
Micron Technology Micron
29F64G08CBAAA Datasheet PDF : 159 Pages
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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Device and Array Organization
Figure 18: Array Organization per Logical Unit (LUN)
Cache Registers
Data Registers
Logical Unit (LUN)
8640 bytes
8640 bytes
8192
448
8192
448
8192
448
8192
448
2048 blocks per plane
4096 blocks per LUN
1 Block
1 Block
Plane 0
(0, 2, 4, ..., 4094)
Plane 1
(1, 3, 5, ..., 4095)
DQ7
DQ0
1 page = (8K + 448 bytes)
1 block = (8K + 448) bytes x 256 pages
= (2048K + 112K1) Bbyltoecs k
1 plane = (2048K + 112K) bytes x 2048 blocks
= 34,560Mb
1 LUN = 34,560Mb x 2 planes
= 69,120Mb
Table 2: Array Addressing for Logical Unit (LUN)
Cycle
First
Second
Third
Fourth
Fifth
DQ7
CA7
LOW
PA7
BA15
LOW
DQ6
CA6
LOW
PA6
BA14
LOW
DQ5
CA5
CA133
PA5
BA13
LOW
DQ4
CA4
CA12
PA4
BA12
LA05
DQ3
CA3
CA11
PA3
BA11
BA19
DQ2
CA2
CA10
PA2
BA10
BA18
DQ1
CA1
CA9
PA1
BA9
BA17
DQ0
CA02
CA8
PA0
BA84
BA16
Notes:
1. CAx = column address, PAx = page address, BAx = block address, LAx = LUN address; the
page address, block address, and LUN address are collectively called the row address.
2. When using the synchronous interface, CA0 is forced to 0 internally; one data cycle al-
ways returns one even byte and one odd byte.
3. Column addresses 8640 (21C0h) through 16,383 (3FFFh) are invalid, out of bounds, do
not exist in the device, and cannot be addressed.
4. BA[8] is the plane-select bit:
Plane 0: BA[8] = 0
Plane 1: BA[8] = 1
5. LA0 is the LUN-select bit. It is present only when two LUNs are shared on the target;
otherwise, it should be held LOW.
LUN 0: LA0 = 0
LUN 1: LA0 = 1
PDF: 09005aef83d2277a
Rev. A 11/09 EN
27
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009 Micron Technology, Inc. All rights reserved.
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