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29F64G08CBAAA View Datasheet(PDF) - Micron Technology

Part NameDescriptionManufacturer
29F64G08CBAAA NAND Flash Memory Micron
Micron Technology Micron
29F64G08CBAAA Datasheet PDF : 159 Pages
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Architecture
Micron Confidential and Proprietary
Advance
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
The commands received at the I/O control circuits are latched by a command register
and are transferred to control logic circuits for generating internal signals to control de-
vice operations. The addresses are latched by an address register and sent to a row
decoder to select a row address, or to a column decoder to select a column address.
Data is transferred to or from the NAND Flash memory array, byte by byte, through a
data register and a cache register.
The NAND Flash memory array is programmed and read using page-based operations
and is erased using block-based operations. During normal page operations, the data
and cache registers act as a single register. During cache operations, the data and cache
registers operate independently to increase data throughput.
The status register reports the status of die (LUN) operations.
Figure 10: NAND Flash Die (LUN) Functional Block Diagram
Vcc Vss Vccq Vssq
Async Sync
DQ[7:0] DQ[7:0]
N/A DQS
I/O
control
Address register
Status register
Command register
CE#
CLE
ALE
WE#
RE#
WP#
CE#
CLE
ALE
CLK
W/R#
WP#
R/B# R/B#
Control
logic
CCoolluummnndDeeccooddee
NNAANNDDFFllaasshh
array A(2rrpalyanes)
DDaattaa rReeggisistteerr
CCaacchhee rReeggisistteerr
Notes: 1. N/A: This signal is tri-stated when the asynchronous interface is active.
2. Some devices do not include the synchronous interface.
PDF: 09005aef83d2277a
Rev. A 11/09 EN
19
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009 Micron Technology, Inc. All rights reserved.
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