|YDA139||STEREO 2.5W DIGITAL AUDIO POWER AMPLIFIER|
|YDA139 Datasheet PDF : 18 Pages |
■Description of operating functions
●Digital Amplifier Function
YDA139 has digital amplifiers with analog and digital input, PWM pulse output, Maximum output of 2.5W(RL=4Ω)×2ch.
Distortion of PWM pulse output signal and noise of the signal is reduced by adopting “Pure Pulse Direct Speaker Drive
First Stage Amplifier Gain Setting Function
YDA139is composed of the first stage amplifier with gain setting control and a 6dB fixed-gain digital amplifier. Gain of the
first stage amplifier can be set by GAIN[1:0] terminal.
Digital Amplifier Gain Setting (Analog Input –Digital Amplifier Output)
Note） H and L indicates logic High and logic Low, respectively.
Connect a 0.01µF or more capacitor to the audio signal input terminals (LIN and RIN) for the rejection of DC signal.
The input low region cutoff frequency is calculated by 1/(2×π×ZIN×CIN).
When GAIN[0:1]=L,L and CIN=0.01µF, the input low region cutoff frequency becomes 159Hz.
And, half voltage (VREF) of AVDD terminal voltage is output to the reference voltage terminals (VREF). Connect a 1µF or
more capacitor to the terminals for voltage stabilization.
*When the input low region cutoff frequency is lowered, capacitor that is larger than 0.01µF (max. 0.1µF) can be
connected. However, please note the following points.
(1) The pop noise when the power supply is disconnected might become large. Therefore, correspond by following method.
①After PDN terminal change to "L", disconnect power supply.
②VREF capacitor is set to CREF=CIN×20[µF].
(2) The recovery time from the power down becomes long. (Refer to the item "Power Down Function" for relation between
the recovery time tPDR and CIN and CREF.)
YDA139 includes a stereo DAC with 44.1kHz, 48kHz/16bit. The output of DAC is amplified by the digital amplifier to
output to speakers. The digital signal input supports the following format.
Gain from DAC output to the digital amplifier output is fixed to 12dB. The full scale voltage (VFS) of DAC is depending on
AVDD terminal voltage (VDDA) and can be found with the following formula: VFS=VDDA×0.56.
VFS is amplified 12dB, and it becomes an amplifier output. For example, VFS=1.68V and amplifier output (BTL) =6.72Vpp
Do not input the DC signal to YDA139 because built-in DAC doesn't have the DC cutting function. And, do not stop each
clock of SCLK, LRCLK and SDIN at the digital input mode and mixing mode.
Digital Signal Input Format (16-bit format with left-justified and a one bit clock delay).
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