|YDA136||STEREO 60W-100W DIGITAL AUDIO POWER AMPLIFIER CONTROLLER|
|YDA136 Datasheet PDF : 32 Pages |
YDA136 operates synchronizing with 4.19MHz clock.
Be sure to connect a 4.16MHz CERALOCK or to supply a clock to YDA136 from the outside.
Be sure to always supply a clock except protection reset mode and hard mute mode.
When using a CERALOCK, be sure to set MSSEL terminal to “L” and to set YDA136 to a master mode.
In case of supplying a clock from the outside, be sure to set MSSL terminal to “H” and to set YDA136 to a slave mode.
Be sure to set MSSEL terminal to “L.”
Connects CELALOCK to XI and XO terminal.
Be sure to set the oscillation frequency to 4.19MHz.
At this time, a master clock (4.19MHz) is output from a MCKIO terminal.
Be sure to set MSSEL terminal to “H.”
Be sure to input a master clock (4.19MHz) into a MCKIO terminal.
At this time, be sure to set XI terminal to “L” and set XO terminal to open state.
When making a multi channel amplifier by using multiple YDA136, a system with little interference between channels can
be constituted by using one YDA136 in master mode, and using the remainder in slave mode as shown in the following
●AM Reception Interference Reduction Function
YDA136 outputs the pulse made by modulating the career clock, which is made by dividing the input master clock.
In order to reduce cross talk caused by the coincidence between harmonics of the output pulse and AM radio frequency,
YDA136 has the changing (frequency hopping) function of two carrier clock frequencies.
A carrier clock frequency can be chosen by the control register CF.
●Off-time Setup Function
A setup of an off-time is individually possible for YDA136
to the High-Side driver and Low-Side driver of Lch and each
Off-time adjustment of the Low-Side driver of Lch and each
Rch is possible by the capacitor that is connected to a
DLYLL terminal and a DLYLR terminal.
Moreover, off-time adjustment of the High-Side driver of
Lch and each Rch is possible by the capacitor connected to a
DLYHL terminal and a DLYHR terminal.
Relation between capacitance value of the capacitor and the
relation of an off-time is shown in the figure.
(Under characteristic adjustment)
Off time delay (Typical)
|Direct download click here|
|Share Link :|