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YTD439 View Datasheet(PDF) - Unspecified

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YTD439 Datasheet PDF : 15 Pages
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Terminal Block
Layer 1 control block
The Layer 1 control block provides the Layer 1 functions conforming to JT-I430.
It automatically controls the Layer 1 state according to (1) the phantom power detection
from the network, (2) the instruction from the host processor and (3) the transaction of
INFO signals and notifies the state change to the host processor. The priority/collision
control block monitors the collision conditions and puts priority on D channel data access
so that each terminal can access the data fairly.
Layer 2 control block
The Layer 2 control block provides the Layer 2 functions (LAP-D protocol) conforming to
JT-Q920 and JT-Q921.
YTD439 can establish total of four data links, two data links for circuit switching and two
data links for D channel packet switching/teleaction communications. It supports the
LAP-D frame assembly and disassembly, the SAPI and TEI address control, the LAP-D
sequence control and flow control for each data link. More specifically, when the YTD439
accepts the data link establishment request from the host processor (Layer 3) in order to
initiate a call or accept an incoming call, the YTD439 activates Layer 1, initiates the TEI
assignment procedure (if necessary), and establishes the data link, thereby enabling the
exchange of layer 3 messages. Later, the YTD439 releases the data link according to the
data link release request from the host processor or the network.
Since both automatic and non-automatic TEI assignment are supported, VC/PVC can be
implemented for packet switching.
Layer 3 Interface Block
The interface between Layer 2 (YTD439) and Layer 3 (host processor) is a logic interface
supporting primitives. The command/status primitives consisting of data up to 8 bytes
are exchanged by writing to or reading from the YTD439 I/O registers to control the data
link.
I frames or UI frames containing Layer 3 messages are transferred using I/O transfer
through the large dedicated FIFO.
B Channel Data Control Block
The B channel data control block consists of two control blocks with the same
functionality for CH-A and CH-B to support the two B channels, B1 and B2. Each B
channel data control block has a HDLC controller block and a transparent block, and the
B channel data FIFO connects to one of the blocks.
You can select the speeds of 128 k, 64 k, or 56 kHz for the HDLC controller block. The
HDLC block supports CRC-CCITT, CRC-32, and no CRC. By activating the HDLC
controller block, protocols such as PPP is also supported.
The transparent block carries out serial-to-parallel conversion on the B channel data and
expands the data in the FIFO. This allows the host processor to check the B channel data
that is received from the line. It also allows transmission of DTMF signals, voice
messages, and other signals to the line by the host processor writing parallel data to the
FIFO. This block also has a flexible rate adaption function that allows the use of protocols
such as V110.
In addition, the transparent block also supports PIAFS64k and PIAFS32k. By following the
commands from the host processor, this block carries out necessary tasks for PIAFS such
as I460 rate adaption, SYNC pattern detection, automatic bit adjustment of 8-bit
boundaries.
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