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XRT91L30 View Datasheet(PDF) - Exar Corporation

Part Name
Description
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XRT91L30 Datasheet PDF : 39 Pages
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xr
REV. 1.0.1
TRANSMITTER SECTION
NAME
LEVEL
TXDI0
TXDI1
TXDI2
TXDI3
TXDI4
TXDI5
TXDI6
TXDI7
LVTTL,
LVCMOS
TYPE
I
TXOP
TXON
LVPECL Diff O
TXPCLK_IO
LVTTL,
I/O
LVCMOS
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
PIN
DESCRIPTION
58 Transmit Parallel Data Input
57 Transmit Parallel Clock Output Operation
56 The 77.76 Mbps (STS-12/STM-4) / 19.44 Mbps (STS-3/STM-1)
55 8-bit parallel transmit data should be applied to the transmit
54
parallel bus and simultaneously referenced to the rising edge of
53
the TXPCLK_IO clock output. The 8-bit parallel interface is mul-
tiplexed into the transmit serial output interface with the MSB
51
first (TXDI[7:0]).
50
Alternate Transmit Parallel Clock Input Operation
When operating is this mode, TXPCLK_IO is no longer a paral-
lel clock output reference but reverses direction and serves as
the parallel transmit clock input reference for the PISO (Parallel
Input to Serial Output) block. The 77.76 Mbps (STS-12/STM-4)
/ 19.44 Mbps (STS-3/STM-1) 8-bit parallel transmit data should
be applied to the transmit parallel bus and simultaneously refer-
enced to the rising edge of the TXPCLK_IO clock input.
5
Transmit Serial Data Output
6
The transmit serial data stream is generated by multiplexing the
8-bit parallel transmit data input into a 622.08 Mbps STS-12/
STM-4 or 155.52 Mbps STS-3/STM-1 serial data stream.
49 Transmit Parallel Clock Input/Output (77.76/19.44 MHz)
Transmit Parallel Clock Output Operation
When the PIO_CTRL pin 48 is asserted "High," this pin will out-
put a 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-
1) clock output reference for the 8-bit parallel transmit data
input TXDI[7:0]. This clock is used by the framer/mapper device
to present the TXDI[7:0] data which the XRT91L30 will latch on
the rising edge of this clock. This enables the framer/mapper
device and the XRT91L30 transceiver to be in synchronization.
Alternate Transmit Parallel Clock Input Operation
When the PIO_CTRL pin 48 is asserted "Low," this pin will
accept a 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/
STM-1) clock input reference for the 8-bit parallel transmit data
input TXDI[7:0]. The XRT91L30 will latch data at TXDI[7:0] on
the rising edge of this clock. This has the enormous advantage
of enabling the framer/mapper device transmit timing to be syn-
chronized with the transceiver transmit timing.
7
 

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