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XRT91L30 View Datasheet(PDF) - Exar Corporation

Part Name
Description
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XRT91L30 Datasheet PDF : 39 Pages
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XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
PIN DESCRIPTIONS
xr
REV. 1.0.1
HARDWARE CONTROL
NAME
RESET
LEVEL
LVTTL,
LVCMOS
TYPE
I
STS12/STS3
LVTTL,
I
LVCMOS
CMUFREQSEL
LVTTL,
I
LVCMOS
PIN
DESCRIPTION
1
Master Reset Input
Active "High." When this pin is pulled "High" , the internal state
machines are set to their default state.
"Low" = Normal Operation
"High" = Master Hardware Reset (100nS minimum)
59 Data Rate Selection
Selects SONET/SDH transmission and reception speed rate
"Low" = STS-3/STM-1 155.52 Mbps
"High" = STS-12/STM-4 622.08 Mbps
3
Clock Multiplier Unit Reference Frequency Select
This pin is used to select the frequency of the REFCLKP/N or
TTLREFCLK input to the CMU.
"Low" = 77.76 MHz reference clock
"High" = 19.44 MHz reference clock
CMU-
FREQSEL
0
STS12/
STS3
0
REFCLKP/N OR
TTLREFCLK
REFERENCE
FREQUENCY
77.76 MHz
0
1
77.76 MHz
1
0
19.44 MHz
1
1
19.44 MHz
DATA RATE
STS-3/STM-1
155.52 Mbps
STS-12/STM-4
622.08 Mbps
STS-3/STM-1
155.52 Mbps
STS-12/STM-4
622.08 Mbps
NOTE: REFCLKP/N or TTLREFCLK input should be generated
from an LVPECL/LVTTL crystal oscillator which has a
frequency accuracy better than 20ppm in order for the
transmitted data rate frequency to have the necessary
accuracy required for SONET systems..
4
 

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