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XRT91L30 View Datasheet(PDF) - Exar Corporation

Part NameDescriptionManufacturer
XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER Exar
Exar Corporation Exar
XRT91L30 Datasheet PDF : 39 Pages
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xr
REV. 1.0.1
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
3.3 Alternate Transmit Parallel Bus Clock Input Option
To decouple transmit parallel clock domains of the framer/mapper device and the XRT91L30 transceiver and to
eliminate difficult timing issues between them, the transmit parallel clock TXPCLK_IO can also be optionally
configured as a clock input. Rather than provide a transmit parallel clock output reference to the framer/mapper
device, the XRT91L30 can instead accept a reference transmit parallel clock input signal from the framer/
mapper device to sample the transmit parallel bus. When PIO_CTRL pin 48 is asserted "Low," TXPCLK_IO
switches into a clock input and the XRT91L30 will now sample data on the transmit parallel bus TXDI[7:0]
based on TXPCLK_IO clock input reference coming from the framer/mapper device. The use of the alternate
transmit parallel bus clock input option permits the system to tolerate an arbitrary amount of phase mismatch
and jitter between framer/mapper transmit parallel clock timing and transceiver transmit timing. Figure 13
provides a detailed overview of the alternate transmit parallel bus clock input system interface.
FIGURE 13. ALTERNATE TRANSMIT PARALLEL INPUT INTERFACE BLOCK (PARALLEL CLOCK INPUT OPTION)
TXDI[7:0]
8
SONET Framer/ASIC
TXPCLK_IO
(Parallel Clock Input Option)
XRT91L30
STS-12/STM-4
or
STS-3/STM-1
Transceiver
PIO_CTRL
CMUFREQSEL
REFCLKN
REFCLKP
TTLREFCLK
3.4 Alternate Transmit Parallel Data Input Timing
When applying parallel data input to the transmitter in the alternate transmit parallel bus clock input mode of
operation, the setup and hold times should be followed as shown in Figure 14 and Table 12, Table 13.
FIGURE 14. ALTERNATE TRANSMIT PARALLEL INPUT TIMING
Transmit Parallel
Clock driven by
Framer/Mapper
Device
TXPCLK_IO
Alternate Transmit Parallel Clock Input Option
tTXPCLK_IO
TXDI[7:0]
tTXDI_SU
tTXDI_HD
23
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