XRT91L30 View Datasheet(PDF) - Exar Corporation

Part Name

Description

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XRT91L30

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

Exar Corporation 

xr

REV. 1.0.1

XRT91L30

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

3.0 TRANSMIT SECTION

The transmit section of the XRT91L30 accepts 8-bit parallel data and converts it to serial Differential LVPECL

data output intented to interface to an optical module. It consists of an 8-bit parallel Single-Ended LVTTL

interface, Parallel-to-Serial Converter, a clock multiplier unit (CMU), a Low Voltage Positive-referenced Emitter-

Coupled Logic (LVPECL) differential line driver, and Loop Timing modes. The LVPECL serial data output rate is

622.08 Mbps for STS-12/STM-4 applications and 155.52 Mbps for STS-3/STM-1 applications. The high

frequency serial clock is synthesized by a PLL, which uses a low frequency clock as its input reference. In

order to synchronize the data transfer process, the synthesized 622.08 MHz for STS-12/STM-4 or 155.52 MHz

STS-3/STM-1 serial clock output is divided by eight and the 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/

STM-1) clock respectively is presented to the framer/mapper device to be used as its timing source.

3.1 Transmit Parallel Input Interface

The parallel data from an framer/mapper device is presented to the XRT91L30 through an 8-bit Single-Ended

LVTTL parallel bus interface TXDI[7:0]. To directly interface to the XRT91L30, the SONET Framer/ASIC must

be synchronized to the same timing source TXPCLK_IO in presenting data on the parallel bus interface. The

data must meet setup and hold times with respect to TXPCLK_IO. This clock output source is used to

synchronize the SONET Framer/ASIC to the XRT91L30. The framer/mapper device should use TXPCLK_IO

as its timing source so that parallel data is phase aligned with the serial transmit data. The data is latched into

a parallel input register on the rising edge of TXPCLK_IO. TXPCLK_IO is derived from a divide-by-8 of the high

speed synthesized clock resulting in a 77.76/ 19.44 MHz Single-Ended LVTTL clock output source to be used

by the framer/mapper device for parallel bus synchronization. A simplified block diagram of the transmit

parallel bus clock output system interface is shown in Figure 11.

FIGURE 11. TRANSMIT PARALLEL INPUT INTERFACE BLOCK

TXDI[7:0]

8

TXPCLK_IO

XRT91L30

STS-12/STM-4

or

STS-3/STM-1

Transceiver

SONET Framer/ASIC

VDD+

PIO_CTRL

CMUFREQSEL

REFCLKN

REFCLKP

TTLREFCLK

21

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