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XRT91L30 View Datasheet(PDF) - Exar Corporation

Part Name
Description
MFG CO.
XRT91L30 Datasheet PDF : 39 Pages
xr
REV. 1.0.1
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
2.10 Receive Parallel Data Output Timing
The receive parallel data output from the STS-12/STM-4 or STS-3/STM-1 receiver will adhere to the setup and
hold times shown in Figure 10 ,Table 7, and Table 8. Table 9 shows the PECL and TTL output timing
specifications.
FIGURE 10. RECEIVE PARALLEL OUTPUT TIMING
RXIP
RXIN
RXPCLKO
tRXCLK
tRXPCLKO
RXDO[7:0] A1
FRAMEPULSE
A2
A2
A2
A2
tRXDO_VALID
tPULSE_WID
TABLE 7: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-12/STM-4 OPERATION)
SYMBOL
tRXCLK
tRXPCLKO
tRXDO_VALID
tPULSE_WID
PARAMETER
Receive high-speed serial clock period
Receive parallel data output byte clock period
Time the data is valid on RXDO[7:0] and FRAMEPULSE
before and after the rising edge of RXPCLKO
Pulse width of frame detection pulse on FRAMEPULSE
MIN
TYP
MAX UNITS
1.608
ns
12.86
ns
4
ns
12.86
ns
TABLE 8: RECEIVE PARALLEL DATA OUTPUT TIMING (STS-3/STM-1 OPERATION)
SYMBOL
tRXCLK
tRXPCLKO
tRXDO_VALID
tPULSE_WID
PARAMETER
Receive high-speed serial clock period
Receive parallel data output byte clock period
Time the data is valid on RXDO[7:0] and FRAMEPULSE
before and after the rising edge of RXPCLKO
Pulse width of frame detection pulse on FRAMEPULSE
MIN
TYP
MAX UNITS
6.43
ns
51.44
ns
22
ns
51.44
ns
19
 

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