XRT91L30 View Datasheet(PDF) - Exar Corporation

Part Name

Description

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XRT91L30

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

Exar Corporation 

XRT91L30

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

xr

REV. 1.0.1

bit de-interleaves the serial data input into an 8-bit parallel output to RXDO[7:0]. A simplified block diagram is

shown in Figure 8. XRT91L30 clocks data out on RXDO[7:0] at the falling edge of RXPCLKO.

FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF SIPO

RXDO0

8-bit Parallel LVTTL Output Data

b03 b02 b01 b00

RXDOn

bn3 bn2 bn1 bn0

RXDOn+

RXDO7

bn+3bn+2 bn+1 bn+0

b73 b72 b71 b70

622.08 Mbps STS-12/STM-4 or

155.52 Mbps STS-3/STM-1 serial data rate

b73 b63 b53 b43 b33 b23 b13

b70 b60 b50 b40 b30 b20 b10 b00 RXIP/N

RXPCLKO

77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)

2.8 Receive Parallel Output Interface

The 8-bit Single-Ended LVTTL running at 77.76 Mbps (STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) parallel

data output of the receive path is used to interface to a SONET Framer/ASIC synchronized to the recovered

clock. A simplified block diagram is shown in Figure 9.

FIGURE 9. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK

SONET Framer/ASIC

RXDO[7:0]

8

RXPCLKO

XRT91L30

STS-12/STM-4

or

STS-3/STM-1

Transceiver

2.9 Disable Parallel Receive Data Output Upon LOS

The parallel receiver outputs are automatically pulled "Low" or forced to a logic state of "0" during a LOS

condition to prevent data chattering unless LOS detection is disabled by asserting DLOSDIS and keeping

LOSEXT input pin "high." In addition, the user can also assert LOSEXT input pin "low" from the optical

module to force an LOS and mute the parallel receiver outputs as well (while DLOSDIS input is also low, see

Figure 7).

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