STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
19 Receive Parallel Data Output
20 77.76 Mbps (STS-12/STM-4) / 19.44 Mbps (STS-3/STM-1)
22 8-bit parallel receive data output is updated simultaneously on
the falling edge of the RXPCLKO output. The 8-bit parallel
interface is de-multiplexed from the receive serial data input
MSB first (RXDO). The XRT91L30 will output the data on
the falling edge of RXPCLKO clock.
13 Receive Serial Data Input
14 The differential receive serial data stream of 622.08 Mbps
STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is applied to
these input pins.
External Recovered Receive Clock Input
The differential receive serial data stream of 622.08 Mbps
STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is sampled on
the rising edge of this externally recovered differential clock
coming from the optical module. It is used when the internal
CDR unit is disabled and bypassed by the CDRDIS pin.
NOTE: In the event that XRXCLKIP/N differential input pins are
unused, XRXCLKIP should be tied to VCC with a 1k
Ohm pull-up and XRXCLKIN should be tied to Ground
with a 1k Ohm pull-down.
29 Receive Parallel Clock Output (77.76 MHz or 19.44 MHz)
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
clock output reference for the 8-bit parallel receive data output
RXDO[7:0]. The parallel received data output bus will be
updated on the falling edge of this clock.
32 Clock and Data Recovery Auxillary Reference Clock
77.76 MHz ± 500 ppm auxillary reference clock for the CDR.
NOTE: In the event that CDRAUXREFCLK LVTTL input pin is
unused, CDRAUXREFCLK should be tied to ground.
11 Out of Frame Input Indicator
This level sensitive input pin is used to initiate frame detection
and byte alignment recovery when OOF is declared by the
downstream device. When this pin is held High, FRAME-
PULSE will pulse for a single RXPCLKO period upon the detec-
tion of every third frame alignment A2 byte in the incoming
"Low" = Normal Operation
"High" = OOF Indication initiating frame detection and byte
boundary recovery and activating FRAMEPULSE
30 Sonet Frame Alignment Pulse
This pin will generate a single pulse for an RXPCLKO clock
period upon the detection of the third frame alignment A2 byte
whenever the OOF input pin is held High. The parallel received
data output bus will then be byte aligned to this newly recov-
ered SONET/SDH frame.