XE1203F View Datasheet(PDF) - Semtech Corporation
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XE1203F Datasheet PDF : 36 Pages
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XE1203F
5 SERIAL INTERFACE DEFINITION AND PRINCIPLES OF OPERATION
5.1 SERIAL CONTROL INTERFACE
A 3-wire bi-directional bus (SCK, SI, SO) is used to communicate with the XE1203F. SCK and SI are input signals
supplied externally, for example by the microcontroller. The XE1203F configures the SO signal as an output pin
during read operation, and it is tri-stated in other modes. The falling edge of the SCK signal is used to sample the SI
pin to write data into the internal shift register of the XE1203F. The rising edge of the SCK signal is used to output
data to SO pin by XE1203F, so the microcontroller should sample data at the falling edge of SCK.
The signal EN must be low during the whole write and read sequences. In write mode the content of the particular
configuration register (see 5.2) is updated on the next rising edge of the EN signal. Before this rising edge, the new
data is stored in temporary registers which do not affect the transceiver settings.
The timing diagram of a write sequence is illustrated in Figure 12 below. The sequence is initiated when a Start
condition is detected, defined by the SI signal being set to “0” during one period of SCK. The next bit is a read/write
(R/W) bit which should be “0” to indicate a write operation. The next 5 bits contain the address of the
configuration/status registers A[4:0] to be accessed, MSB first (see 5.2). Then, the next 8 bits contain the data to be
written into the register. The sequence ends with 2 stop bits set to “1”. The data on SI should change on the rising
edges of SCK, and is sampled on the falling edge of SCK. After the 2 stop bits, the data transfer is terminated. The
SI line should be at “1” for at least one extra SCK clock cycle before a new write or read sequence can start. This
mode of operation allows data to be written into multiple registers keeping the EN line low.
The maximum frequency of SCK is 1 MHz, except as defined above when reading the RSSI or FEI outputs, where
the maximum frequency of SCK is limited to 100 kHz. The minimum clock pulse width is 0.5 us. Over the operating
supply and temperature range, set-up and hold time for SI on the falling edge of SCK are 200 ns.
The register at address 0 is one bit long. When writing this register, the sequence described above is valid except
that only one data bit is required instead of 8. However, if a single write procedure is used for all registers 8 data bits
must be sent when writing at address 0, but only the MSB will be stored at address 0. The remaining 7 data bits
must all be “1”.
sck
si
A(4) A(3) A(2) A(1) A(0) D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
/en
so
High impedance
Figure 12: Write sequence into configuration register
Figure 13 illustrates a write sequence at address zero.
© Semtech 2007
www.semtech.com
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