XE1202A View Datasheet(PDF) - Semtech Corporation

Part Name

Description

View to exact match

XE1202A

433 MHz / 868 MHz / 915 MHz Low-Power, Integrated UHF Transceiver

Semtech Corporation 

XE1202A TrueRF™

RTParam_FEI

en

fei_out

datain

XX

VAL1

VAL2

VAL3

VAL4

XX

DataOut_FEI

XX

VAL2

VAL4

TS_FE

Figure 4: FEI measurement timing diagram when “RTParam_Fsel” = 1

4.1.4.2 “RTParam_Fsel” = 0

With the “RTParam_FEI” bit set to “1” and the RTParam_Fsel” bit set to “0”, the FEI function uses over sampling of

the signal at the output of the demodulator. When activated by the rising edge of DATAIN, this function provides an

8-bit word equivalent to the duty cycle of the demodulated preamble, stored in register “DataOut_FEI”.

Each sample is used to control an up/down counter, when the sample is "1" the content of the counter is

incremented, when the sample is "0" the content of the counter is decremented. As a consequence, the final 8-bit

value of the counter stored in “DataOut_FEI” gives an indication of the duty cycle of the demodulated signal. The

range of stored values is from -128 and +127. The further from 0 the value of DataOut_FEI, the higher the error on

the LO frequency. If the stored value in “DataOut_FEI” is typically zero, then the duty cycle of the preamble is about

50 %, and the LO frequency is nominally correct.

Since this FEI uses the signal before the bit synchronizer, its value can vary from one measurement to another,

due to the presence of jitter and glitches in the signal. If possible, it is advised to make 4-5 measurements and take

the average value.

The timing diagram for this FEI measurement is illustrated in Figure 5 below. The FEI function is activated at the

rising edge of the /EN signal when the RTParam_FEI bit is set to “1”. Then, the internal FEI counter is activated at

the rising edge of DATAIN. After a period TS_FE equal to the duration of 4 bits (see Electrical Specifications), the

counter is stopped and the contents are stored in the register DataOut_FEI. For a proper operation, the pulse

length on DATAIN has to be higher than 8µs.

The maximum delay between the rising edge of DATAIN and the first clock on the internal FEI counter is 1/(16*BR),

where BR is the bit rate.

© Semtech 2006

13

www.semtech.com

Share Link: