4285GZ View Datasheet(PDF) - Intersil
Part Name
Description
View to exact match
4285GZ Datasheet PDF : 22 Pages
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X4283, X4285
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as 64 bytes per page.
The device features an 2-wire interface and software
protocol allowing operation on an 2-wire bus.
PIN CONFIGURATION
8-Pin JEDEC SOIC
S0 1
S1 2
RST/RST 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
8-Pin TSSOP
WP 1
VCC 2
S0 3
S1 4
8 SCL
7 SDA
6 VSS
5 RST/RST
PIN DESCRIPTION
Pin
(SOIC)
1
2
3
Pin
(TSSOP)
3
4
5
4
6
5
7
6
8
7
1
8
2
Name
S0
S1
RESET/
RESET
VSS
SDA
SCL
WP
VCC
Function
Device Select Input
Device Select Input
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever VCC falls below the minimum VCC sense level. It will remain ac-
tive until VCC rises above the minimum VCC sense level for 250ms. RESET/RESET
goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW
longer than the selectable Watchdog time out period. A falling edge on SDA, while
SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes active on power-up
and remains active for 250ms after the power supply stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. This pin requires a pull up resistor and the input buffer is al-
ways active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the
control register.
Supply Voltage
2
FN8121.1
May 23, 2006
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