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X1227F 데이터 시트보기 (PDF) - Intersil

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X1227F 2-Wire™ RTC Real TimeClock/Calendar/CPU Supervisor with EEPROM Intersil
Intersil Intersil
X1227F Datasheet PDF : 28 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PIN DESCRIPTIONS
X1227
X1
X2
RESET
VSS
X1227
8 LD SOIC
1
8
2
7
3
6
4
5
VCC
VBACK
SCL
SDA
NC = No internal connection
VBACK
VCC
X1
X2
X1227
8 LD TSSOP
1
8
2
7
3
6
4
5
SCL
SDA
VSS
RESET
PIN ASSIGNMENTS
Pin Number
SOIC
TSSOP
1
3
2
4
3
5
4
6
5
7
6
8
7
1
8
2
Symbol
X1
X2
RESET
VSS
SDA
SCL
VBACK
VCC
Brief Description
X1. The X1 pin is the input of an inverting amplifier and should be connected to one
pin of a 32.768kHz quartz crystal.
X2. The X2 pin is the output of an inverting amplifier and should be connected to
one pin of a 32.768kHz quartz crystal..
Reset Output – RESET. This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or that the voltage has
dropped below a fixed VTRIP threshold. It is an open drain active LOW output.
VSS.
Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of
the device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs.
Serial Clock (SCL). The SCL input is used to clock all data into and out of the
device. The input buffer on this pin is always active (not gated).
VBACK. This input provides a backup supply voltage to the device. VBACK supplies
power to the device in the event the VCC supply fails. This pin can be connected to
a battery, a Supercap or tied to ground if not used.
VCC.
3
FN8099.2
May 8, 2006
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