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X1226V8 데이터 시트보기 (PDF) - Intersil

부품명X1226V8 Intersil
Intersil Intersil
상세내역4K (512 x 8), 2-Wire™ RTC
X1226V8 Datasheet PDF : 25 Pages
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Figure 4. Valid Start and Stop Conditions
X1226
SCL
SDA
Start
Figure 5. Acknowledge Response From Receiver
SCL from
Master
1
Data Output
from Transmitter
Data Output
from Receiver
Start
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to either the EEPROM
array or to the CCR. Slave bits ‘1010’ access the
EEPROM array. Slave bits ‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the cus-
tomer to a known state.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the
operation to be performed. When this R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 6.
After loading the entire Slave Address Byte from the
SDA bus, the X1226 compares the device identifier
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Stop
8
9
Acknowledge
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power-
up the internal address counter is set to address 0h,
so a current address read of the EEPROM array starts
at address 0. When required, as part of a random
read, the master must supply the 2 Word Address
Bytes as shown in Figure 6.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in
the “read” section. That is if the random read is from
the array the slave byte must be 1010111x in both
instances. Similarly, for a random read of the
Clock/Control Registers, the slave byte must be
1101111x in both places.
11
FN8098.3
May 8, 2006
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DESCRIPTION
The X1226 device is a Real Time Clock with clock/calendar, two polled alarms with integrated 512x8 EEPROM, oscillator compensation, and battery backup switch.

Real Time Clock/Calendar with EEPROM
FEATURES
• Real Time Clock/Calendar
   —Tracks Time in Hours, Minutes, and Seconds
   —Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
   —Settable on the Second, Minute, Hour, Day of the Week, Day, or Month
   —Repeat Mode (periodic interrupts)
• Oscillator Compensation On Chip
   —Internal Feedback Resistor and Compensation Capacitors
   —64 Position Digitally Controlled Trim Capacitor
   —6 Digital Frequency Adjustment Settings to ±30ppm
• Battery Switch or Super Cap Input
• 512 x 8 Bits of EEPROM
   —64-Byte Page Write Mode
   —8 Modes of Block Lock™ Protection
   —Single Byte Write Capability
• High Reliability
   —Data Retention: 100 Years
   —Endurance: 100,000 Cycles Per Byte
• 2-Wire™ Interface Interoperable with I2C
   —400kHz Data Transfer Rate
• Frequency Output (SW Selectable: Off, 1Hz, 4096Hz or 32.768kHz)
• Low Power CMOS
   —1.25µA Operating Current (Typical)
• Small Package Options
   —8 Ld SOIC and 8 Ld TSSOP
• Repetitive Alarms
• Temperature Compensation
• Pb-Free Plus Anneal Available (RoHS Compliant)

APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive

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