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X1205V8Z View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
X1205V8Z 2-Wire™ RTC Real Time Clock/Calendar Intersil
Intersil Intersil
X1205V8Z Datasheet PDF : 22 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
X1205
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
tWC
Stop
Condition
Start
Condition
Power-up Timing
Symbol
Parameter
Min.
Typ.(2)
Max.
Units
tPUR(1)
tPUW(1)
Time from Power-up to Read
Time from Power-up to Write
1
ms
5
ms
Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are not 100% tested.
VCC slew rate should be between 0.2mV/µsec and 50mV/µsec.
(2) Typical values are for TA = 25°C and VCC = 5.0V
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
Note:
tWC(1)
Write Cycle Time
5
10
ms
(1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
6
FN8097.2
September 23, 2005
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