INTERNAL POWER ON RESET CIRCUIT
Figure 2 Internal Power on Reset Circuit Schematic
The WM8850 includes an internal Power-On-Reset Circuit, as shown in Figure 2, which is used to
reset the digital logic into a default state after power up. The POR circuit is both powered from and
monitors DCVDD. It asserts the internal R¯¯E¯S¯E¯T¯ low if DCVDD is below a minimum threshold.
Figure 3 Typical Power up Sequence
Figure 3 shows a typical power-up sequence. The R¯¯E¯S¯E¯T¯ signal is undefined until DCVDD has
exceeded the minimum threshold, Vpor_active. Once this threshold has been exceeded, R¯¯E¯S¯E¯T¯ is
asserted low and the chip is held in reset. In this condition, all stimulus to the WM8850 is ignored.
Once DCVDD has reached Vpor_on, R¯¯E¯S¯E¯T¯ is released high, all registers are in their default state and
access to the WM8850 via the HDA Interface may take place.
On power down, R¯¯E¯S¯E¯T¯ is asserted low whenever DCVDD drops below the minimum threshold
Typical Power-On Reset parameters for the WM8850 are defined in Table 2.
MIN TYP MAX UNIT
Table 2 Typical Power-On Reset parameters
PP, April 2011, Rev 3.2