3D7110 View Datasheet(PDF) - Data Delay Devices

Part Name

Description

View to exact match

3D7110

MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7110)

Data Delay Devices 

3D7110

APPLICATION NOTES (CONT’D)

custom reference designator identifying the

intended frequency and duty cycle of operation.

The programmed delay accuracy of the device is

guaranteed, therefore, only for the user specified

input characteristics. Small input pulse width

variation about the selected pulse width will only

marginally impact the programmed delay

accuracy, if at all. Nevertheless, it is strongly

recommended that the engineering staff at

DATA DELAY DEVICES be consulted.

POWER SUPPLY AND

TEMPERATURE CONSIDERATIONS

The delay of CMOS integrated circuits is strongly

dependent on power supply and temperature.

The monolithic 3D7110 programmable delay line

utilizes novel and innovative compensation

circuitry to minimize the delay variations induced

by fluctuations in power supply and/or

temperature.

The thermal coefficient is reduced to 600

PPM/C, which is equivalent to a variation , over

the 0C-70C operating range, of ±3% from the

room-temperature delay settings and/or 1.0ns,

whichever is greater. The power supply

coefficient is reduced, over the 4.75V-5.25V

operating range, to ±1% of the delay settings at

the nominal 5.0VDC power supply and/or 1.5ns,

whichever is greater. It is essential that the

power supply pin be adequately bypassed

and filtered. In addition, the power bus

should be of as low an impedance

construction as possible. Power planes are

preferred.

DEVICE SPECIFICATIONS

TABLE 2: ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL MIN

MAX UNITS NOTES

DC Supply Voltage

Input Pin Voltage

Input Pin Current

Storage Temperature

Lead Temperature

VDD

VIN

IIN

TSTRG

TLEAD

-0.3

7.0

V

-0.3

VDD+0.3

V

-1.0

1.0

mA

25C

-55

150

C

300

C

10 sec

TABLE 3: DC ELECTRICAL CHARACTERISTICS

(0C to 70C, 4.75V to 5.25V)

PARAMETER

SYMBOL MIN

Static Supply Current*

IDD

High Level Input Voltage

VIH

2.0

Low Level Input Voltage

VIL

High Level Input Current

IIH

Low Level Input Current

IIL

High Level Output Current

IOH

-4.0

Low Level Output Current

IOL

4.0

Output Rise & Fall Time

TR & TF

MAX

30

0.8

1

1

2

UNITS

mA

V

V

µA

µA

mA

mA

ns

NOTES

VIH = VDD

VIL = 0V

VDD = 4.75V

VOH = 2.4V

VDD = 4.75V

VOL = 0.4V

CLD = 5 pf

*IDD(Dynamic) = 10 * CLD * VDD * F

where: CLD = Average capacitance load/tap (pf)

F = Input frequency (GHz)

Input Capacitance = 10 pf typical

Output Load Capacitance (CLD) = 25 pf max

Doc #96005

DATA DELAY DEVICES, INC.

4

12/2/96

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

Share Link: