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W49V002AP View Datasheet(PDF) - Winbond

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W49V002AP Datasheet PDF : 32 Pages
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Timing Waveforms for LPC Interface Mode, continued
Toggle Bit Timing Diagram
Preliminary W49V002A
CLK
#RESET
#LFRAM
LAD[3:0]
CLK
#RESET
Memory
Write
1st Start Cycle
Address
Data
TAR
Sync
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] A[15:12]
A[11:8]
A[7:4]
A[3:0] D[3:0] D[7:4]
1111b Tri-State 0000b
TAR
1 Clock 1 Clock
Load Address "An" in 8 Clocks
Load Data "Dn"
in 2 Clocks
2 Clocks 1 Clock
Write the last command(program or erase) to the device in LPC mode.
#LFRAM
LAD[3:0]
CLK
#RESET
Start
0000b
Memory
Read
Cycle
010Xb A[31:28]
A[27:24]
Address
A[23:20] A[19:16] XXXXb XXXXb
XXXXb
XXXXb
TAR
Sync
1111b Tri-State 0000b
Data
XXXXb X,D6,XXb
TAR
1 Clock1 Clock
Load Address in 8 Clocks
2 Clocks 1 Clock Data out 2 Clocks
Read the DQ6 to see if the internal write complete or not.
#LFRAM
LAD[3:0]
Start
0000b
Memory
Read
Cycle
010Xb A[31:28]
A[27:24]
Address
A[23:20] A[19:16] XXXXb XXXXb
XXXXb XXXXb
TAR
Sync
1111b Tri-State 0000b
Data
XXXXb X,D6,XXb
TAR
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks 1 Clock Data out 2 Clocks
When internal write complete, the DQ6 will stop toggle.
All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
Start next
command
1 Clock
Next Start
0000b
1 Clock
Next Start
0000b
1 Clock
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Publication Release Date: April 2001
Revision A1
 

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